More specifically, integrated circuit design decisions are often driven by device scalability, device density, manufacturing efficiency and costs. For example, size scaling of planar field effect transistors (FETs) resulted in the development of planar FETs with relatively short channel lengths and, unfortunately, the smaller channel lengths resulted in a corresponding increase in short channel effects and a decrease in drive current. In response, non-planar FET technologies (e.g., fin-type FET (FINFET) technologies) were developed. A FINFET is a non-planar FET that incorporates a semiconductor fin (i.e., a relatively tall and thin, elongated, rectangular-shaped, semiconductor body) and, within the semiconductor fin, a channel region positioned laterally between source/drain regions. A gate is positioned adjacent to the top surface and opposing sidewalls of the semiconductor fin at the channel region. Such a FINFET exhibits two-dimensional field effects as compared to the single-dimensional field effects exhibited by a planar FET and, thus, exhibits increased drive current. It should be noted that, because the semiconductor fin is so thin, any field effects exhibited at the top surface are insignificant (i.e., negligible). To further increase drive current, multiple parallel semiconductor fins can be incorporated into a single FINFET.
As device size scaling continues, designers have achieved optimal FINFET performance with semiconductor fins and, particularly, channel regions made of materials other than silicon. For example, III-V compound semiconductor materials (e.g., indium phosphide (InP), gallium arsenide (GaAs), etc.) are optimal for N-type FET (NFET) performance and germanium and silicon germanium with a high germanium percentage are optimal for P-type FET (PFET) performance. However, the use of silicon substrates is still desirable in terms of manufacturing efficiency and cost. Therefore, techniques have been developed for forming silicon semiconductor fins on a silicon substrate, covering the silicon fins with a dielectric layer, performing a polishing process (e.g., a chemical mechanical polishing (CMP) process) to expose the tops of the silicon fins, selectively removing the silicon fins and then performing an expitaxial growth process in order to replace the silicon fins with monocrystalline semiconductor fins made of some other semiconductor material. Unfortunately, due to lattice mismatch between the silicon substrate that acts as the seed layer and the epitaxial semiconductor material of the replacement semiconductor fins, defects can occur and can propagate throughout the replacement semiconductor fins so as to negatively impact device performance.